Phase detector circuits are commonly used to detect a phase difference between two input signals. One typical application is in a phase locked loop (PLL) to detect a phase difference between a reference signal from a reference oscillator and a loop feedback signal. The output of the phase detector circuit is used to adjust the phase relationship between the reference signal and output signal of the PLL.
One phase detector circuit includes two D-type flip flops, a delay element and an AND gate. The D inputs of the flip flops are tied to a high logic level. One flip flop is clocked by a reference signal, the other flip flop is clocked by a feedback signal from a voltage controlled oscillator (VCO) of a PLL. The outputs of the flip flops are ANDed together and the result delayed in the delay element, then used to reset one of the flip flops. The other flip flop is reset with the result from the AND gate without being delayed. Each flip flop enables a charge pump. One charge pump provides a positive current to the VCO, the other charge pump provides negative current to the VCO. Charge is added to correct phase mismatch between the reference signal and the feedback signal.
This phase detector circuit is generally adequate for most applications. However, there is still an imbalance of charge added to or subtracted from the VCO by the charge pumps, particularly near in-phase condition. The result is phase noise. The amount of phase noise can be unacceptable in certain applications, such as in a fractional-n synthesizer. To optimize the phase noise of the fractional-n synthesizer, equal amounts of charge must be added and subtracted from the loop for a given phase offset. The prior art phase detector circuit has been inadequate for this purpose.
Accordingly, there is a need in the art for a phase detector which provides equal amounts of charge to the loop near the in-phase condition.